In increasing performance of a FET, it is known that gate dielectric reliability vs. Tinv scaling is a major industry trade-off. For example, increasing the thickness of a dielectric material stack increases reliability of the semiconductor device, but this increase in stack thickness will also decrease performance. Conversely, decreasing the thickness of a dielectric material stack can decrease reliability of the semiconductor device, but this decrease in stack thickness will also increase performance.
Also, as MOSFET devices are scaled down to less than 100 nanometers in gate or channel length, highly doped, shallow source and drain extension regions can be employed to achieve high drive current capability. The dopants are activated by conducting laser annealing or other millisecond-scale (mSec) annealing of the implanted extension regions either prior, during, or after a more conventional, second-scale Rapid Thermal Anneal (RTA).